Design Verification Engineer (287658)
3900 N Capital of Texas Hwy Austin, TX 78746
Key Responsibilities Include:
• Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers of the Coherent fabric and LPDDR memory controller.
• Develop test plans, test benches and tests, creating sequencers, drivers, checkers, and monitors in a UVM environment.
• Enhance test benches and tests to achieve coverage goals.
• Create and support test environments for different design hierarchy levels.
• Support unit and super-unit debug on simulation platforms.
• BSEE, Computer Engineer or comparable and 2+ years of experience.
• Experienced with verification methodology such as UVM/VMM/OVM.
• Developed test plans of complex systems containing multiple state machines and protocol rules.
• Composed functional coverage assertions, preferably using System Verilog.
Preferred candidate will possess the following:
• Exposure to either CPU coherency protocols or DDR memory controllers.
• ARM-ACE Coherency or LPDDR4/5 experience would be a bonus.
• Proficient in System Verilog, C++, and Python/Perl scripting.
• Excellent verbal and written communication skills.