Arch Staffing
http://www.archstaffingandconsulting.com
http://www.archstaffingandconsulting.com
Design Verification Engineer (287658)
3900 N Capital of Texas Hwy Austin, TX 78746
Posted: 10/28/2020
2020-10-28
2021-02-25
Industry: Engineering
Job Number: 4172
Job Description
We are currently looking for exceptional software and hardware talent to join our R&D Center, and our Advanced Computing Lab one of our investments in high performance low power ARM based device technology. Presently our GPU design teams are developing a GPU that will be deployed in mobile products. We are working on Coherent Interconnect and memory controller architectures. As a Design Verification Engineer you will contribute to the functional verification of ARM-AMBA Coherent fabrics and LPDDR4/5 memory controllers. This is a hands-on role, driving next generation product development with a high level of contribution and knowledge base needs.
Key Responsibilities Include:
• Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers of the Coherent fabric and LPDDR memory controller.
• Develop test plans, test benches and tests, creating sequencers, drivers, checkers, and monitors in a UVM environment.
• Enhance test benches and tests to achieve coverage goals.
• Create and support test environments for different design hierarchy levels.
• Support unit and super-unit debug on simulation platforms.
Minimum Requirements:
• BSEE, Computer Engineer or comparable and 2+ years of experience.
• Experienced with verification methodology such as UVM/VMM/OVM.
• Developed test plans of complex systems containing multiple state machines and protocol rules.
• Composed functional coverage assertions, preferably using System Verilog.
Preferred candidate will possess the following:
• Exposure to either CPU coherency protocols or DDR memory controllers.
• ARM-ACE Coherency or LPDDR4/5 experience would be a bonus.
• Proficient in System Verilog, C++, and Python/Perl scripting.
• Excellent verbal and written communication skills.
Key Responsibilities Include:
• Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers of the Coherent fabric and LPDDR memory controller.
• Develop test plans, test benches and tests, creating sequencers, drivers, checkers, and monitors in a UVM environment.
• Enhance test benches and tests to achieve coverage goals.
• Create and support test environments for different design hierarchy levels.
• Support unit and super-unit debug on simulation platforms.
Minimum Requirements:
• BSEE, Computer Engineer or comparable and 2+ years of experience.
• Experienced with verification methodology such as UVM/VMM/OVM.
• Developed test plans of complex systems containing multiple state machines and protocol rules.
• Composed functional coverage assertions, preferably using System Verilog.
Preferred candidate will possess the following:
• Exposure to either CPU coherency protocols or DDR memory controllers.
• ARM-ACE Coherency or LPDDR4/5 experience would be a bonus.
• Proficient in System Verilog, C++, and Python/Perl scripting.
• Excellent verbal and written communication skills.